A conventional processing accelerator may be implemented as a programmable logic device (PLD), such as a Field Programmable Gate Array (FPGA) or a Graphics Processing Unit (GPU), to provide efficient accelerator logic. Data-center and mobile-device applications are increasingly data-intensive and for such an application that utilizes a processing accelerator, a conventional memory hierarchy is unable to provide good performance and energy efficiency. The maximum efficiency of a processing accelerator in a conventional memory hierarchy is degraded by off-chip (i.e., non-CPU) memory accesses. Implementing accelerator logic close to memory to improve efficiency has thus far provided limited success because of high costs and sub-optimal performance. Further, if the accelerator logic is implemented close to memory, such as dynamic random access memory (DRAM), DRAM capacity is forfeited by integrating non-DRAM accelerator logic onto a DRAM semiconductor die.
Generally, a programmable logic device (PLD) is an electronic component that is used to form reconfigurable digital circuits. Unlike a logic gate or logic circuit, which generally has a fixed function, a PLD traditionally has an undefined function at the time of manufacture and often before the PLD can be used in a circuit, the PLD must be programmed, or reconfigured, to perform a desired function.
Traditionally, a PLD may include a combination of a logic device and a memory device. The memory is generally used to store a programming pattern that defines a desired function. Most of the techniques used for storing data in an integrated circuit have been adapted for use in a PLD, such as silicon anti-fuses, static random access memory (SRAM), erasable programmable read only memory (EPROM), electronically EPROM (EEPROM), non-volatile RAM, etc. Most PLDs generally include components that are programed by applying a special voltage (i.e., non-operational or high voltage) across a modified area of silicon inside the PLD that breaks or sets (depending on the technology) electrical connections and changes the layout of the electrical circuit of the PLD.
One of the most common types of PLDs is a field-programmable gate array (FPGA), which is an integrated circuit that is designed to be configured by a customer or a designer after manufacturing; hence the term “field-programmable.” An FPGA includes an array of programmable logic blocks, and a hierarchy of reconfigurable interconnects that allow the blocks to be “wired together”. The logic blocks of an FPGA can be configured to perform complex combinational functions, or merely simple logic gates like AND, XOR, etc.